Multiported memories provide an effective mechanism for access by a plurality of users to a memory. Such multiported memories avoid problems inherent with single bus access. These memories or multiported memory arrangements may be used in combination with high performance real time/imbedded processor designs. However with these designs, it is often very desirable or even necessary to guarantee low latency to one or more critical users of the multiported memory. Low latency guarantees may be achieved through the use of a multilevel memory arbitration.
Multilevel arbitration schemes, wherein different access priority levels are set, can result in periods when there is extremely high memory access latency for low priority users. Specifically, to provide the low latency guarantee for the critical users of the memory, the low priority users suffer.
Certain high performance processors and application specific devices have bus interface units that queue memory operations. In a multilevel arbitration scheme providing access to the critical users of the memory, the non-critical users can get shut out for long periods of time. Specifically, the critical memory users are able to assert the next memory request as soon as the present operation is completed. When the next request to the target memory occurs within the arbitration window of the target memory, the high priority user again has access to the memory. This can result in the high priority user being granted many contiguous accesses or back-to-back accesses.
With the scheme as described above, multiple contiguous accesses can result which impose a very high latency for low priority users. Ultimately, the high latency for the low priority users results in a negative impact on system performance.
Instead of providing a multilevel memory arbitration, a more complex arbitration scheme can be implemented. This can be effective in reducing the latency problem. However, these solutions may be to gate intensive to implement without semi-custom or custom ASICs (application specific integrated circuits). Such complex arbitration schemes may be difficult to tune for optimal performance. This is bparticularly true if the memory control/arbitration device is used in varying applications.